During the process of forming integrated circuits on a compound semiconductor wafer, more or less stress is accumulated such that the compound semiconductor wafer is suffered a stress. In some certain situation, the compound semiconductor wafer is suffered greater stress, such as forming a stressed thin film on the compound semiconductor wafer or growing a stressed epitaxial structure on the compound semiconductor wafer. If the stress suffered by the compound semiconductor wafer cannot be properly balanced, then it will cause bowing distortion of the compound semiconductor wafer. Even further it will crack the edge of the compound semiconductor wafer. Moreover, after the compound semiconductor wafer thinning process, since the compound semiconductor wafer becomes thinner so that it is more difficult for balancing the stress suffered by the compound semiconductor wafer. Therefore, the bowing distortion of the compound semiconductor wafer becomes more serious and even further causes the cracking of the edge of the compound semiconductor wafer.
In terms of the diameters of the compound semiconductor wafers, the bowing distortion of the compound semiconductor wafer caused by the stress is less obvious when the diameter of the compound semiconductor wafer is less than 3 inches, while the bowing distortion of the compound semiconductor wafer caused by the stress is much more significant when the diameter of the compound semiconductor wafer is greater than or equal to 3 inches, such as 4 inches, 5 inches, 6 inches or even greater.
In conventional technology, an improved structure is disclosed for balancing the stress suffered by the silicon semiconductor wafer. Please refer to FIG. 3, which is a sectional schematic view of an improved structure for silicon semiconductor wafer of conventional technology. An integrated circuit 11 is formed on a top surface 101 of a silicon semiconductor wafer 10. A stress balance layer 12 is formed on a bottom surface 102 of the silicon semiconductor wafer 10 for balancing the stress which is accumulated during the process of forming the integrated circuit 11 and suffered by the silicon semiconductor wafer 10.
In the application of compound semiconductor devices, growing multiple layers of epitaxial structure is needed during the formation of the integrated circuits on the compound semiconductor wafer. Comparing to forming silicon based integrated circuits on a silicon semiconductor wafer, usually the compound semiconductor wafer is suffered much more stress than the silicon semiconductor wafer. However, the conventional technology does not disclose the stress balance structure which can effectively balance the stress suffered by a compound semiconductor wafer. Furthermore, for some certain application of compound semiconductor devices, it is required to form a metal layer or to form an ohmic electrode on a bottom surface of a compound semiconductor wafer. The improved structure for silicon semiconductor wafer of the conventional technology could not meet the requirement.
Moreover, for some certain application of compound semiconductor devices, especially for high power devices, the heat dissipation is a very important issue. The heat generated by high power devices has to be dissipated. Therefore, when the improved structure for reducing compound semiconductor wafer distortion (including the balancing the stress layer) is designed to be formed on the bottom of the compound semiconductor wafer, a better design of the balancing the stress layer is required to have a high thermal conductivity such that the heat can be dissipated through the bottom of the compound semiconductor wafer to a package substrate.
Accordingly, the present invention has developed a new design which could avoid the above mentioned drawbacks, may significantly enhance the performance of the devices and may take into account economic considerations. Therefore, the present invention then has been invented.